Multiple layer floating gate non-volatile memory devices are described in US-A-2009/0140317. In such devices, the floating gate comprises at least two layers constructed in different conductive or semiconductive materials. An intermediate dielectric layer of a predetermined thickness is used to separate at least two of the layers of floating gate to enable a direct tunnelling current between the two separated layers.
When implementing planar non-volatile memory cells, program saturation can be an important factor for designing various elements of the non-volatile memory cells. For non-volatile memory cells at sub-20 nm “node” in which half-pitch of the memory cells are sub-20 nm, unwanted fringing capacitances can lead to unacceptable levels of cell-to-cell interference and loss of gate coupling ratio (GCR).
For lateral scaling of NAND planar flash memory cells below about the 20 nm node, in order to reduce the effects cell-to-cell interference, and because of lack of physical space between neighbouring cells, a fully planar cell architecture has been proposed, where the control gate is no longer wrapped around the floating gate. One drawback of the planar cell architecture is a large reduction of the GCR, whose effect includes a reduction in the threshold voltage (Vth) window. This reduction in the Vth window can partially be mitigated by using a hybrid floating gate, where a high work-function metal is formed on top of the silicon (Si) floating gate. Such a structure limits the leakage through the inter-gate dielectric during programming, and therefore enables a larger programming window. Such a hybrid floating gate cell with a floating gate comprising a titanium nitride (TiN) metal layer on a poly-Si layer is disclosed, for example, in IEEE Electron Device Letters Vol. 33, no.3, March 2012, pages 333-335 by P. Blomme et al. “Hybrid floating gate cell for sub-20-nm NAND flash memory technology”. In this reference, the inter-gate dielectric of choice was aluminium oxide (Al2O3), a material with a k-value of about 8. However, a higher k inter-gate dielectric is still required in order to increase the coupling ratio and allow further voltage scaling. The inter-gate dielectric also needs to have low leakage in order to avoid charge loss and program saturation which is due to charge passing through the inter-gate dielectric during the programming operation. To this end, a high-k/low-k materials combination can reduce the charge flow through the inter-gate dielectric by increasing the tunnelling distance at the floating gate side during programming.
U.S. Pat. No. 7,989,871 describes embodiments of non-volatile memory devices which comprise a substrate, a tunnel dielectric, a floating gate, an interfacial layer, an inter-gate dielectric and a control gate arranged as layers in ascending order on the substrate. Various combinations of materials are disclosed for these devices together with layer thicknesses.